Hi Rijohn: I am encountering an issue while adapting our hardware’s Flash( S25FL128LAGBHM023 ) configuration for the AM2612 processor and would appreciate your guidance. Problem Description: When configuring the OSPI Flash protocol to 1s1s4s , the AM2612 incorrectly sets the mode to 1s4s4s . The OSPI_FLASH_CFG_DEV_INSTR_WR_CONFIG_REG Register[13:12] and OSPI_FLASH_CFG_DEV_INSTR_RD_CONFIG_REG Register [13:12] are both set to 0x02 (indicating 4s mode) instead of the expected 0x01 (1s mode). Temporary Fix in ospi_flash_dma Example: Manually modifying these register bits resolved the issue. Issue Persists in sbl_jtag_uniflash Example: Despite manually updating the OSPI_FLASH_CFG_DEV_INSTR_WR_CONFIG_REG Register [13:12] to 0x00 , the configuration does not take effect. Confirmed via CCS Memory view that the register value remains unchanged or reverts after modification. Questions: Why does the manual register modification work in the ospi_flash_dma example but fail in sbl_jtag_uniflash ? Could there be a configuration override or timing issue in the SBL bootloader flow? Additional Context: Mcu: XAM2612AODFHMZCZQ1 Sdk: mcu_plus_sdk_am261x_10_00_01_10 Register Addresses: OSPI_FLASH_CFG_DEV_INSTR_WR_CONFIG_REG Register: [address, 0x53808008] OSPI_FLASH_CFG_DEV_INSTR_RD_CONFIG_REG Register: [Insert address, 0x 53808004 ] The attachment is syscfg Manually modified code is called after Board_driversOpen() int32_t OSPI_lld_norFlashInit1s1s4s(OSPILLD_Handle handle) { int32_t status = OSPI_SYSTEM_SUCCESS; volatile uint32_t regVal = 0U; /* Check if the handle is NULL */ if(NULL != handle) { const CSL_ospi_flash_cfgRegs *pReg = (const CSL_ospi_flash_cfgRegs *)(handle->baseAddr); /* Wait for a while */ // uint32_t waitMicro = 500U * 1000U; // handle->Clock_usleep(waitMicro); /* SDR will be enabled in flash by default, set OSPI controller to 1S-1S-1S mode */ uint32_t xferLines = 0; /* Set RD and WR Config register */ regVal = CSL_REG32_RD(&pReg->DEV_INSTR_RD_CONFIG_REG); /* Configure the Device Read Instruction Configuration Register */ regVal &= ~(CSL_OSPI_FLASH_CFG_DEV_INSTR_RD_CONFIG_REG_INSTR_TYPE_FLD_MASK | \ CSL_OSPI_FLASH_CFG_DEV_INSTR_RD_CONFIG_REG_RD_OPCODE_NON_XIP_FLD_MASK | \ CSL_OSPI_FLASH_CFG_DEV_INSTR_RD_CONFIG_REG_ADDR_XFER_TYPE_STD_MODE_FLD_MASK | \ CSL_OSPI_FLASH_CFG_DEV_INSTR_RD_CONFIG_REG_DATA_XFER_TYPE_EXT_MODE_FLD_MASK | \ CSL_OSPI_FLASH_CFG_DEV_INSTR_RD_CONFIG_REG_DDR_EN_FLD_MASK | \ CSL_OSPI_FLASH_CFG_DEV_INSTR_RD_CONFIG_REG_DUMMY_RD_CLK_CYCLES_FLD_MASK); regVal |= (((uint32_t)0x6B) DEV_INSTR_RD_CONFIG_REG, regVal); xferLines = 0; regVal = CSL_REG32_RD(&pReg->DEV_INSTR_WR_CONFIG_REG); /* Configure the Device Write Instruction Configuration Register */ regVal &= ~(CSL_OSPI_FLASH_CFG_DEV_INSTR_WR_CONFIG_REG_DUMMY_WR_CLK_CYCLES_FLD_MASK | \ CSL_OSPI_FLASH_CFG_DEV_INSTR_WR_CONFIG_REG_WR_INSTR_RESV3_FLD_MASK | \ CSL_OSPI_FLASH_CFG_DEV_INSTR_WR_CONFIG_REG_WR_OPCODE_FLD_MASK | \ CSL_OSPI_FLASH_CFG_DEV_INSTR_WR_CONFIG_REG_DATA_XFER_TYPE_EXT_MODE_FLD_MASK | \ CSL_OSPI_FLASH_CFG_DEV_INSTR_WR_CONFIG_REG_ADDR_XFER_TYPE_STD_MODE_FLD_MASK | \ CSL_OSPI_FLASH_CFG_DEV_INSTR_WR_CONFIG_REG_DUMMY_WR_CLK_CYCLES_FLD_MASK); regVal |= (((uint32_t)0x02) DEV_INSTR_WR_CONFIG_REG, regVal); /* Set read capture delay */ // status += OSPI_lld_setRdDataCaptureDelay(handle, 0); } else { status = OSPI_SYSTEM_FAILURE; } return status; } Please let me know if further details are required. Thank you for your support! This issue is urgent, please follow up as soon as possible Best regard zx
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