Part Number: TMS320F280039 Tool/software: Hi, i would like to raise a question about specific FSI-RX module behaviour. We have a FSI fsi daisy-chain configuration, that is fully initiialized (handshaked) and transmitting frames. On any received data frame we trigger the DMA for copying 16 data-words into a buffer. There are some bit-errors on the physical line, which is why we need to confirm the behaviour of the FSI in the following cases. 1. When the FSI-RX core detects a CRC mismatch, is the DMA trigger still executed? We do see the error irq generated and CRC-error flag is set, which is handled by the ISR. We need to know if the DMA is still supposed to copy the FSI-RX-buffer into RAM? If yes, is it possible to prevent that behaviour? 2. The note in TRM page 3173 clearly says, that the RX-module needs to undergo a reset and resync with the transmitter in case of a CRC-mismatch. However, that specific condition is not mentioned in chapter 31.3.3.10 (Conditions in Which the Receiver Must Undergo a Soft Reset). Does the FSI-RX require a reset on CRC-error? 3. Is the CRC-calcuation (and error irq) still executed, when RX-UDATA-filtering is active and a non-matching (different UDATA) frame is received? Thanks for answering in advance. Best regards, Felix
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