Hi Chirs, [quote userid="631335" url="~/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1479821/mspm0g3507-hard-fault-when-running-images-built-with-the-gnu-arm-toolchain/5767052#5767052"]Is it true that polling CPUSS->CTL returns the actual state of the corresponding caches?[/quote] Yes, it does. Used with this code is for the timing. After it disabled cache, it requires several CPU cycles to fully disable the bit. This additional code could make sure the cache is disabled before accessing the factory region. That the only cases I can imagine that trigger Hardfault. [quote userid="631335" url="~/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1479821/mspm0g3507-hard-fault-when-running-images-built-with-the-gnu-arm-toolchain/5767052#5767052"]Is there some documentation on what happens in detail when a cache or prefetch gets disabled? If so, where? [/quote] Sorry, there is no official documents for this detail timing clarification. It is too low level of the digital logic. B.R. Sal
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