Hi Sal, [quote userid="631335" url="~/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1479821/mspm0g3507-hard-fault-when-running-images-built-with-the-gnu-arm-toolchain/5713556#5713556"] The TRM doesn't indicate that reading CPUSS->CTL would return the actual state of the corresponding caches. As such, I would not expect to read back anything different from what was written to it previously. Apparently that's not true. The TRM also doesn't say what happens in detail when a cache or prefetch gets disabled. Can you shed some light on this or point me to other documentation that does? [/quote] Sorry for the delay, but I didn't feel that the responses above are answering my questions. Maybe I misunderstood. Is it true that polling CPUSS->CTL returns the actual state of the corresponding caches? Is there some documentation on what happens in detail when a cache or prefetch gets disabled? If so, where? Regards, Chris.
↧