Forum Post: MSP430FR5969: Clock system is selecting MCO instead of HFXT; HFXT continually in fault

Part Number: MSP430FR5969 Tool/software: Hi All, I've seen a couple of threads about this, but they all come back to "read the TI example code" and then silence... In short - I've got an MSP430FR5969 with a 16MHz crystal (not oscillator) connected to the HFXT pins. When enabling the HFXT, I invariably end up with SMCLK and MCLK running from MODCLK (~4.8MHz) instead, and HFXTOFFG set to 1 permanently (cannot be cleared). Code: PJSEL0 |= BIT4 | BIT5 | BIT6 | BIT7; // For XT1 and XT2 // Disable the GPIO power-on default high-impedance mode to activate // previously configured port settings PM5CTL0 &= ~LOCKLPM5; CSCTL0_H = CSKEY >> 8; // Unlock CS registers CSCTL1 = DCORSEL | DCOFSEL_4; // Set DCO to 8MHz CSCTL2 = SELA__VLOCLK | SELS__HFXTCLK | SELM__HFXTCLK; CSCTL3 = DIVA__1 | DIVS__1 | DIVM__1; // Set all dividers to 1 CSCTL4 = HFXTDRIVE_3 | HFFREQ_2; CSCTL4 &= ~(HFXTOFF); CSCTL5 &= ~ENSTFCNT1; do { CSCTL5 &= ~(LFXTOFFG | HFXTOFFG); // Clear XT1 and XT2 fault flag SFRIFG1 &= ~OFIFG; }while (SFRIFG1&OFIFG); // Test oscillator fault flag CSCTL0_H = 0; // Lock CS registers Compared to the TI example (msp430fr69xx_cs_04.c), my changes are: Line 8 - changed the DCO to 16MHz. This works fine, if I run everything from the DCO then there are no problems. Line 9 - selected the HFXTCLK instead of DCOCLK to drive MCLK, and fall-back to DCOCLK when HFXT is unavailable. Selected the VCOCLK for ACLK since I don't have a LFXT. Line 11 - removed the LFXTDRIVE setting as unnecessary. Added the HFFREQ setting, which TI's example seems to skip completely (leaving it set on the 16 - 24MHz range with an 8MHz crystal, which shouldn't work at all). Line 12 - only force the HFXT to always-on mode, as the LFXT is not fitted. Line 13 - disable the LFXT startup counter since there's no LFXT. These all seem like pretty sensible changes to make. Very nearly all of them are essential since the LFXT is not present. Running this code just results in the SMCLK and MCLK running at ~4.8MHz, and the loop at the end (waiting for the fault flag to clear) never completes. Any ideas? I'm awfully tempted to just blame the hardware, which is always possible, but other people seem to have posted similar problems and then found a workaround (or at least gone silent). Thanks in advance!