Part Number: TMS320F2809 Tool/software: I do not understand whether the GPIO outputs (when configured as simple GPO) are on , off , or unknown , after a reset. The language around figure 4-17 in System Control and Interrupts (SPRU712H) confuses me. My primary concern is the possibility a GPO could reset into the on state, until it is explicitly turned off in the software. This would be odd behavior, and I want to make sure it isn't possible. Above figure 4-17, it says "a reset will clear all bits and latched values to zero." This suggests the GPADAT register bits are set to zero and electrical outputs are set to zero. But note #1 says the "... state of the GPADAT register is unknown after reset [and] depends on the level of the pin after reset." How should one read this? What level? Does the environment (electrical level) decide the state of the data register bit and, therefore, what value it drives after reset ?
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