Dear Masoud Farhadi, Your proposed method is as follows: a) CPU1 reads the trim values in the OTP region of CPU1 and stores them in a shared memory area(ex. GSxRAM) accessible by CPU2. b) CPU2 reads the trim values from the shared memory and applies it to the ADC TRIM registers (ADCOFFTRIM, ADCINLTRIM1~6). Is the reason for your proposal that there could be potential issues if CPU1 applies the trim value to the ADC module and then hands over ownership to CPU2, which subsequently activates ADCCTL1[ADCPWDNZ] and operates the ADC module? To apply your proposed method to my firmware, I would not be able to use the AdcSetMode( ) function provided by TI. Instead, I would need to manually implement similar code to initialize the ADC. Since there is a risk of making mistakes in this process, I would prefer to use a TI-validated solution if possible. If there is any documentation or example code that provides a precise initialization procedure for CPU2 (Slave Core) to operate the ADC module within the electrical specifications outlined in the datasheet, I would appreciate receiving it. Thanks and regards, Sang-il
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