[quote userid="554226" url="~/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1486770/tms320f28388d-accessing-peripheral-result-by-both-the-cores-simultaneously"] 1. Can the both cores access the eCAP result (ECap3Regs.CAP1) at the same time? If they access at same time, what can happen to the result read by both the cores as it can trigger ecap event at same time to both the cores? [/quote] Both cores cannot access the eCAP result at the same time. Which core has access to the peripheral registers will be determined by the CPUSEL register. Please refer to this e2e thread: https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/881378/tms320f28379d-access-to-the-peripherals For example, if CPU1 owns eCAP1, then only CPU1 will be able to read from the eCAP registers. CPU2 will read back 0's. Even though both cores can be triggered by the same interrupt source. [quote userid="554226" url="~/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1486770/tms320f28388d-accessing-peripheral-result-by-both-the-cores-simultaneously"] 2. If I have configured the same interrupt in both the events like ecap3_isr,adc_isr,pwm_isr then do I need to acknowledge in both the cores like below? [/quote] Yes each CPU has their own PIPE. Thus, making sure to get the next interrupt on each core means you'll need to acknowledge both. [quote userid="554226" url="~/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1486770/tms320f28388d-accessing-peripheral-result-by-both-the-cores-simultaneously"]If adc result is read by CPUs, before the result ready or during conversion, will it be previous value or random value?[/quote] The ADC results are duplicated for each CPU, CLA, and DMA so that no arbitration is needed when reading the result registers. If ADC result is read by CPUs before the result is read, it will contain previous value. Best, Ryan Ma
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