Hi Ralph, I took the epwm_synchronization example and did the following examples in sequential order. TBCLK = 200MHz / (8*1) = 25MHz -> Ttbclk = 40ns. Compared EPWM0 -> EPWM1 synchronization. 1. Set EPWM1 to no phase shift. Changes: EPWM1 Phase Shift Value(TBPHS)=0. epwm_synchronization.c::Line146 change ClockP_sleep(5) -> (500) Result: EPWM1 lags EPWM0 by 40ns=1xTBCLK As mentioned up counter with TBCLK count up Result: EPWM1 lag 40ns=1xTBCLK 3. Changing TBCLK to 200MHz. Result: EPWM1 lags 10ns=2xTBCLK This confirms your comments above. That the 2xlag is due to the TBCLK=EPWMCLK. It does not depend on SYNCDIR or clock mode. Thanks for clarifying how the sync works. 2 Questions: Is this an expected chip functionality? I did not see this behavior mentioned in TRM nor the Errata. When using CMPD to generate SYNCOUT for EPWM0 using up/down counter, is the sync pulse generated on the up count or down count? And is this configurable? Thanks PS. I have decided to not use the sync feature at all and simply ensure all TBCTRs are zero'd when TBCLKs are enabled during initialization. Just would be nice to understand how sync works in case we need to sync during operation mode.
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