Hi Anjana, Thanks for sharing the details, some points from my side: 1. Multi-core ethernet on MCU is complex because of current SW design and complexity. 2. Ambiguity in configuration, so by design it is recommended that only 1 core configure CPSW. Both cores should not access CPSW registers simultaneously. TI has some existing solutions (EthFW model) for multicore CPSW but that are not available for MCUs with no plans in near future to support it. EthFW design allows one core to be CPSW master and other are CSPW client cores (not present on AM26x MCUs). In EthFW, Master does all CSPW config, via IPC, clients send info to master if they want to change configuration. 3. On MCUs, this model is not available. ( software-dl.ti.com/.../ethfw_c_ug_top.html) There are two ways to proceed here: 1. Implement EthFW model to let Core-3 be Master and Core-4 be Client (open only DMA Channel by hardcoding flow ID). Call Enet DMA related functions wherever required. This might be complex, according to current roadmap, there are no plans to support this on AM26x MCUs. So this has to be driven on your end. 2. Based on some packet content, transfer the packets to other R5F core. Let one core handle all CPSW configs, transfer data to other core based on some packet content via IPC or LwIP bridge. One core does all the config and CPSW handling, other core can do data processing. This might add some software overhead but this is one possible and less complex solution. Regards, Shaunak
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