Apologies for the lack of reply. The line of code you have underlined is not related to the hwbist change in return address, but rather some internal code we place if there is need to modify the boot ROM by using TI OTP to jump around a code section. We place these throughout the BROM in case we find issues after release, so that we can address them in SW, vs releasing a new device for a full ROM change. The code that performs the action you are talking about is right below this at address at line 156 ; if((HwbistRegs.CSTCRET.all != 0)) then branch to address. Let me know if this is clears things up. cpu1brom_hwbist_reset_check: ; ; if((CpuSysRegs.RESC.bit.HWBIST & 0x1) == 1) then check CSTCRET ; MOVW DP, #0x174e ;Set DP to CpuSysRegs.RESC AND AL, @0x0, #0x20 ;Load ACC with (CpuSysRegs.RESC & 0x20) which is HWBIST RESC bit LSR AL, 5 ;Right shift ACC (HWBIST RESC bit) value by 5 TBIT @AL, #0x0 ;Check bit 0 of ACC value (HWBIST RESC) SBF cpu1brom_hwbist_reset_done, NTC ;Branch if reset bit not set ; ; CPU1 Patch/Escape Point 1 ; MOVL XAR4, #0x703ECU ;Load CPU1BROM_TI_OTP_ESCAPE_POINT_1 OTP address MOVL XAR5, *+XAR4[0] ; ; if((EntryAddr != 0xFFFFFFFF) && (EntryAddr != 0x00000000)) ; MOVB ACC, #0 SUBB ACC, #1 CMPL ACC, XAR5 SBF cpu1brom_hwbist_reset_no_escape, EQ MOVL ACC, XAR5 SBF cpu1brom_hwbist_reset_no_escape, EQ LCR *XAR5 ; ((void (*)(void))EntryAddr)(); ; ; if((HwbistRegs.CSTCRET.all != 0)) then branch to address ; cpu1brom_hwbist_reset_no_escape: EALLOW MOVW DP, #0x1780 ;Set DP to HwbistRegs MOVL ACC, @0x34 ;Load HwbistRegs.CSTCRET.all EDIS SBF cpu1brom_hwbist_reset_done, EQ ;Branch if CSTCRET is ZERO MOVW DP, #0 ;CPU1BROM_bootStatus DP MOVW @0x2, #0x8001 ;Update lower boot status (set boot start, boot complete) MOVW @0x3, #0x8000 ;Update upper boot status (HWBIST handled) MOVL XAR5, ACC ;Set CSTCRET value as return address SPM #0 LCR *XAR5 ;Branch to address ; ; Reset cause isn't from HWBIST or CSTCRET is zero ; Best, Matthew
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