I believe the issue here is the interpretation of the signal graph. This trigger pulse is coming from outside the ADC domain, either from the EV module, SW, or ext GPIO pin. In any case all of these signals are in the SYSCLK domain(likely 150MHz). Once these are presented to the ADC clock, it will be latched on the next rising edge, and then be cleared and take the cycles shown. For an external signal this simply needs to meet the GPIO qualification requirements(dependent on how the GPIO is configured, either SYNC or with a qualification time). The internal logic will take care of holding the signal until it is latched by the ADC, regardless of the source. I would not use ASYNC mode on the GPIO input here as it will further complicate things in terms of latching this signal. [quote userid="642069" url="~/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1473404/tms320f2812-external-adc-soc-input-for-tms320f2812/5673631#5673631"]Hi Ben, I would rephrase my question as follows: from the instant SOC trigger input goes high, to the instant where sample and hold begins, the minimum time it will take would be 2.5 ADC clock cycles. But depending on where in ADC clock cycle the SOC trigger input went high, it could also go upto 3.5 ADC clock cycles?[/quote] This is correct, worst case the trigger comes right after a rising edge of ADC clock, so it will take an additional ADC clock(3.5 total) before the signal gets latched into the ADC. Best case it comes right before a rising edge an we get 2.5 ADC shown. I think Ben has clarified this, but from an external signal POV it is a rising edge triggered event, again from the GPIO setting, the diagram is showing from the falling edge of the latched signal presented to the ADC, likely to give some indication of the above(but I agree this diagram could be more clear). Best, Matthew
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