Rijohn, Tejas, Thank you for the detailed responses. I see the use case for connecting OSPI0_RESET_OUT0 by logic OR gate, and will note it going forwards. >> I think if this were to happen, the ROM bootloader would fail to read OSPI flash then attempt to load the SBL, which is fine > Can you please elaborate on the above? Sure I can be clearer. We set Boot mode pins to OSPI Read with UART fallback. I think the worst case scenario would be if the AM263 issues a command to erase a flash sector, then AM263 resets. That would trigger the flash to reset by WARMRSTn output, and the flash chip should take 1s to recover from reset. During that 1s period, I believe the flash chip will not respond to *any* commands. So In that case I expect the RBL attempt to read the SBL from all 4 fallback addresses and fail every time because the flash chip is not responding. Then I expect RBL to switch to UART fallback boot mode; from there we can recover the system.
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