[quote userid="566966" url="~/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1452133/am263p4-q1-setting-sop-pins-to-4s-mode-not-working/5592288#5592288"] "OSPI controller supports only SPI mode 0 [bits 2:0](CPHA=0, CPOL =0) in SDR" This is not true. When power on the mcu, I could capture the SPI traffic on bus, which is running at SPI mode 3 (CPOL = 1, CPHA = 1). Which means RBL configured OSPI in mode 3. [/quote] Hi Phoenix, Thank you correcting me. Yes, ROM does configure in SPI MODE = 3 in case of OSPI (4s) boot mode. Section 5.4.1.3.1 OSPI (4S) Bootloader Operation in AM263P TRM explains this. And on checking the value Bit [2:1] in Octal-SPI Configuration Register (0x538080 00 ) it is 2'b11 indicating that it is in MODE 3 Mode 0 and Mode 3 is supported in SDR and In DDR mode, supported SPI Mode is mode 0. [quote userid="566966" url="~/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1452133/am263p4-q1-setting-sop-pins-to-4s-mode-not-working/5592288#5592288"]The issue is RBL cannot load code from ext flash at 4S mode. If as you said that one of your customer could boot in 1s-1s-4s mode, can we have the information of chip connections? As this is not related with our SW, it is about RBL.[/quote] Our customers have used MX25L3233F QSPI Flash and they were able to boot in 1s-1s-4s mode. One difference which was observed in SW is the Quad enable bit configuration in MX25L3233F and S25FL128S flashes. S25FL128S have CR[1] as the QE enable bit ( Non-Volatile ). We would need to set this bit from applications before the initial boot(for the 1st time). Quad Data Width (QUAD) CR1[1]: When set to 1, this bit switches the data width of the device to 4 bit -Quad mode. That is, WP# becomes IO2 and HOLD# becomes IO3. The QUAD bit must be set to one when using Read Quad Out (6Bh) command. Can you please try configuring the Quad Enable bit as per the commands provided in section 8.5.2 Configuration Register 1 (CR1) ,section 10.3.7 Write Registers (WRR 01h) of flash datasheet and using STIG mode in OSPI as per AM263P TRM section 13.3.3.6.4.11 OSPI Software-Triggered Instruction Generator (STIG) We are trying to replicate the hardware setup from our end. Our SW team will be working on this. Debug is in progress and will keep you posted on the update of debug. Thanks & Regards, Rijohn
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