Forum Post: TMS570LS1224: Functional Safety - Potential for JTAG Port to influence MCU in operation

Part Number: TMS570LS1224 Tool/software: Hi all, i'm conducting a HW FMEDA (not MCU-FMEDA) and got to the point where i look at the effects of short circuits between the debug pins of the MCU to GND, VCC and to neighbouring pins. The question is, what happens if a debug interface pins voltage level changes during operation? For example, looking at TMS: TMS is not connected externally and has an internal Pull-Up, so i would expect, that a short to VCC (VIO Level) should not lead to a failure during operation. but what happens if there is a short to GND? What effect, if any, would this have on the MCUs operation? Is there any documentation i could refer to, to get an answer to this? Especially as i'm trying to determine the effects of faults at any of the debug pins. Kind Regards, Lukas