Part Number: TMS320F28388D Tool/software: Hello - I have an application where a received FSI frame is used to trigger an FSI frame transmit. The FSI RX tag match signal is routed straight through a CLB with no logic, then to a pin via the CLB output xbar, and back into the input XBAR to the FSI TX external trigger. With this configuration I'm observing nondeterministic timing between the trigger signal at the GPIO pin and the start of data transmission. The below capture is triggered in the GPIO FSI trigger signal and shows the FSI TX data line with some persistence. There are 5 district edges with 5ns spacing which seems to indicate that the transmitter synchronizes the the external trigger signal to PLLRAWCLK (200MHz) and then there is some delay until the next TXCLK (20MHz) edge. Given that distributed synchronization is one of the apparent use cases of the FSI interface, this nondeterministic behavior seems highly undesirable. Is there an FSI configuration that achieves deterministic delay in this use case? Thanks, Mark
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