Part Number: TMS320F28379D Tool/software: Hello, I'm currently using the TMS320F28379D in a current design. This question is specific to SCI 'address-bit mode' implementation vs typical 'idle-mode'. We currently support idle-mode only which has been sufficient for our customer base. The code is operating very well w/o issue. A new customer uses SCI/UART with address-bit mode implemented in their UART scheme and would like us to support -if able. Note: Our design adheres to a strict master/slave arrangement; we are the slave device and never take control of the bus. We only act when the first byte received, which by our spec definition, is the address byte matches our pre-programmed address. So, we do not need to change anything other than to support the extra bit added to the frame. During Init: The previous SCICCR was set to: 0x0067 (idle-mode, 1stop bit, no loopback, even parity, 8databits, async mode) The previous SCICTL1 was set to 0x0003 (sleep, tx-wake, rx-enable, tx-enable) The previous SCICTL2 was set to 0x0003 (receive-ready, break-detect, transmit-ready, tx-empty) To support address-bit mode, the NEW SCICCR register value is set to: 0x006F which sets b[3] (multiprocessor mode control bit). No other changes were made from above. Our first try with above change was unsuccessful. Are there any other changes that should be made that we missed? Do we need to explicitly disable sleep mode when the address matches? Thank you in advance for your thoughts/input.
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