Yes, this is the expected behavior with the external circuit shown. As VDDIO begins to ramp the internal POR logic does not start functioning until ~0.6V as you have noted. Even though XRSn is rising during this time it does not meet the device VIH requirements for what is considered "logic high" so the device itself is still not out of reset and no code will be executed, etc. Once the POR logic comes active it will hold reset off until the device is in the proper operational range such that both VDDIO is within DS spec and VDD(from the internal VREG) is also in spec. So, there should be no system impact to the above waveform, and the device is always kept in a known state. Best, Matthew
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