Part Number: TMS320F28377D Tool/software: Dear All I'am using EMIF of F28337D to exchange data with a FPGA . The EMIF is configued in asynchronous memory mode and the wait mode is disabled. In https://www.ti.com/lit/pdf/SPRUHM8 Table 25-21, it says, quote On the rising edge of the clock that is concurrent with the end of the strobe period: • EM1OE rises • The data on the EM1Dx bus is sampled by EMIF. To my knowledge there should be a minimal data hold time after EM1OE rises, then I found this value in TMS320F2837xD Dual-Core Real-Time Microcontrollers datasheet (Rev. P) ,. No.13 row in above figure says the hold time can be 0 ns, which is a bit opposed with my intuition. Now I'am going to implement a FPGA design to achieve an asynchronous Read/Write mechinism , like an asynchronous SRAM, as a slave device of F28377D. So, my questions are: 1. When DSP read data from FPGA, should FPGA keep EMxD signal stable for some non-zero time after EMxOE rises? According to the specification of F28377D, the answer seems to be no. Could anyone help confirm it?
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