Hi Prarthan, I understand that the cycle count cannot be suggested, but my queiry was more related the qualification to be synced to the clock or not. If we add in the cycle qualification , then can the qualification mode still be ASYNC? For example, Is the below valid? // GPIO42->GPIO->nFault GPIO_setMasterCore(42, GPIO_CORE_CPU1); GPIO_setPinConfig(GPIO_42_GPIO42); GPIO_setDirectionMode(42, GPIO_DIR_MODE_IN); GPIO_setPadConfig(42, GPIO_PIN_TYPE_PULLUP); // GPIO40 to GPIO47 , qualification period set to 2.55 us GPIO_setQualificationPeriod(40,510); //Set mode to ASYNC GPIO_setQualificationMode(42, GPIO_QUAL_ASYNC); -->Is this correct?? OR we are now forced to use either 3 or 6 sample window(which is no longer ASYNC) // GPIO42->GPIO->nFault GPIO_setMasterCore(42, GPIO_CORE_CPU1); GPIO_setPinConfig(GPIO_42_GPIO42); GPIO_setDirectionMode(42, GPIO_DIR_MODE_IN); GPIO_setPadConfig(42, GPIO_PIN_TYPE_PULLUP); // GPIO40 to GPIO47 , qualification period set to 2.55 us GPIO_setQualificationPeriod(40,510); // set mode to 3-sample: Sample window width = 2*2.55 = 5.1 us GPIO_setQualificationMode(42, GPIO_QUAL_3SAMPLE); -->Is this correct??
↧
