The V2A_CTL_REG has SDRAM_IDX and REGION_IDX parameters to define the available memory you have on the board. This allows the DDR wrapper to identify out of range address fetches, and sets the AERR bit if an address is out of range. As an example, if you have a 2GB DDR memory on your board, this register should be set to 0x1EF (ie, SDRAM_IDX=0xF, REGION_IDX=0xF). These values are reflected in the output of the DDR Register Configuration Tool https://dev.ti.com/sysconfig/?product=Processor_DDR_Config&device=AM64x Regards, James
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