Hi Luke, I have one doubt: should the location where from I call flash API functions be also in SARAM? I checked again and I saw that it is not true in my code but was in the TI Flash programming example. If there was such a constraint why is it required? What is the rationale? Regards, Piotr Romaniuk PS Flash API in this processor is in ROM: abs 003ffef3 _Flash2806x_APIVersionHex abs 003ffebd _Flash2806x_Erase abs 003ffebb _Flash2806x_Program abs 003ffee7 _Flash2806x_ToggleTest abs 003ffedf _Flash2806x_Verify Linker script (the project folder also contains standard F2806x_Headers_nonBIOS.cmd): /* // TI File $Revision: /main/3 $ // Checkin $Date: March 3, 2011 13:45:44 $ //########################################################################### // // FILE: F28062.cmd // // TITLE: Linker Command File For F28062 Device // //########################################################################### // $TI Release: $ // $Release Date: $ //########################################################################### */ /* ====================================================== // For Code Composer Studio V2.2 and later // --------------------------------------- // In addition to this memory linker command file, // add the header linker command file directly to the project. // The header linker command file is required to link the // peripheral structures to the proper locations within // the memory map. // // The header linker files are found in \F2806x_headers\cmd // // For BIOS applications add: F2806x_Headers_BIOS.cmd // For nonBIOS applications add: F2806x_Headers_nonBIOS.cmd ========================================================= */ /* Define the memory block start/length for the F2806x PAGE 0 will be used to organize program sections PAGE 1 will be used to organize data sections Notes: Memory blocks on F28062 are uniform (ie same physical memory) in both PAGE 0 and PAGE 1. That is the same memory region should not be defined for both PAGE 0 and PAGE 1. Doing so will result in corruption of program and/or data. Contiguous SARAM memory blocks can be combined if required to create a larger memory block. */ MEMORY { PAGE 0 : /* Program Memory */ /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */ RAML0 : origin = 0x008000, length = 0x000800 /* on-chip RAM block L0 */ OTP : origin = 0x3D7800, length = 0x000400 /* on-chip OTP */ FLASHB : origin = 0x3F4000, length = 0x002000 /* on-chip FLASH */ FLASHA : origin = 0x3F6000, length = 0x001F80 /* on-chip FLASH */ CSM_RSVD : origin = 0x3F7F80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */ BEGIN : origin = 0x3F7FF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */ CSM_PWL_P0 : origin = 0x3F7FF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */ ROM : origin = 0x3FF3B0, length = 0x000C10 /* Boot ROM */ RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */ VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */ PAGE 1 : /* Data Memory */ /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */ /* Registers remain on PAGE1 */ BOOT_RSVD : origin = 0x000000, length = 0x000050 /* Part of M0, BOOT rom will use this for stack */ RAMM0 : origin = 0x000050, length = 0x0003B0 /* on-chip RAM block M0 */ // RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ DRAML1 : origin = 0x008800, length = 0x000400 /* on-chip RAM block L1 */ DRAML2 : origin = 0x008C00, length = 0x005400 /* ram 21k */ //RAML2 : origin = 0x008C00, length = 0x005400 /* ram 21k */ //RAML2 : origin = 0x008C00, length = 0x000400 /* on-chip RAM block L2 */ //RAML3 : origin = 0x009000, length = 0x001000 /* on-chip RAM block L3 */ //RAML4 : origin = 0x00A000, length = 0x002000 /* on-chip RAM block L4 */ //RAML5 : origin = 0x00C000, length = 0x002000 /* on-chip RAM block L5 */ USB_RAM : origin = 0x040000, length = 0x000800 /* USB RAM - not used */ } /* Allocate sections to memory blocks. Note: codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code execution when booting to flash ramfuncs user defined section to store functions that will be copied from Flash into RAM */ SECTIONS { /* Allocate program areas: */ .cinit : > FLASHA, PAGE = 0 .pinit : > FLASHA, PAGE = 0 .text : > FLASHA, PAGE = 0 codestart : > BEGIN, PAGE = 0 ramfuncs : LOAD = FLASHA, RUN = RAML0, LOAD_START(_RamfuncsLoadStart), LOAD_END(_RamfuncsLoadEnd), RUN_START(_RamfuncsRunStart), LOAD_SIZE(_RamfuncsLoadSize), PAGE = 0 /*#ifdef __TI_COMPILER_VERSION - not used #if __TI_COMPILER_VERSION >= 15009000 //.TI.ramfunc : {} LOAD = FLASHD, .TI.ramfunc : {} LOAD = FLASHA, RUN = RAML0, LOAD_START(_RamfuncsLoadStart), LOAD_END(_RamfuncsLoadEnd), RUN_START(_RamfuncsRunStart), PAGE = 0 #endif #endif*/ //keys and reserved area csmpasswds : > CSM_PWL_P0, PAGE = 0 csm_rsvd : > CSM_RSVD, PAGE = 0 /* Allocate uninitalized data sections: */ .stack : > RAMM0, PAGE = 1 .ebss : > DRAML1, PAGE = 1 .esysmem : > DRAML1, PAGE = 1 /* Initalized sections to go in Flash */ .econst : > FLASHA, PAGE = 0 .switch : > FLASHA, PAGE = 0 /* .reset is a standard section used by the compiler. It contains the */ /* the address of the start of _c_int00 for C Code. /* /* When using the boot ROM this section and the CPU vector */ /* table is not needed. Thus the default type is set here to */ .reset : > RESET, PAGE = 0, TYPE = DSECT vectors : > VECTORS, PAGE = 0, TYPE = DSECT } /* //=========================================================================== // End of file. //=========================================================================== */
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