[quote userid="605914" url="~/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1404398/tms320f28388d-tms320f28388d---hwbist-synchronization-and-semaphore-management-for-cpu-cores"] Is there any mechanism for CPU1 to block CPU2 until the BIST operation is complete and then send a command to CPU2 to start its operation once the semaphore is released from CPU1? [/quote] Reading the semaphore status from CPU2 until you see CPU1 release it is one option. I believe the claim semaphore function in the SDL returns whether or not the claim was successful, so you could probably just call it periodically until it returns a success without needing to write to GS RAM. Alternatively you could leverage an IPC flag to tell CPU2 to block until CPU1 signals that it is done with HWBIST. [quote userid="605914" url="~/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1404398/tms320f28388d-tms320f28388d---hwbist-synchronization-and-semaphore-management-for-cpu-cores"]Is there a limitation preventing CPU2 from writing data to GS0? If so, please suggest a solution for storing BIST status (excluding flash memory).[/quote] See the "Global Shared RAM (GSx RAM)" section in the TRM. You can configure each GS RAM to be owned by either CPU, but when one CPU is the owner, the other CPU loses write access. Have you scene our Multicore Development Guide ? Whitney
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