Hi Raghu, I see, yes in that case you would have to use a 1-byte (1/16) FIFO trigger level since there is no timeout interrupt on the SCI receiver. This configuration is basically the same as if you disabled the FIFO. I would suggest keeping the SCI RX ISR very short in this case and avoiding having too many other higher priority interrupts that could block the SCI RX ISR, as both of these things could cause data loss. You can also enable the RXERROR interrupt and check the error flags inside the SCI RX ISR during debugging to ensure no overrun/data loss occurs with this setup. Best Regards, Delaney
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