Hello JM, Please expect delay in response due to MLK holiday. The 8192 INTOSC1 cycles is for circuit to determine loss of OSCCLK (which can be INTOSC2 or XTAL/X1). As soon as it detects loss of OSCCLK, NMI is generated and you can configure PWM actions in ISR. [quote userid="563423" url="~/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1311453/tms320f28379d-undesirable-issue-with-pwm-trip-and-frequency-when-utilizing-missing-clock-detection-mcd/4988935#4988935"]Can you confirm whether this is the expected behaviour of the PWM during an external clock failure before the NMI ISR causes the PWM to trip?[/quote] There should be no change in pwm frequency before CLOCKFAIL is generated. All the actions ( NMI generation, PWM trip, Switch to INTOSC1) are taken at same time after loss has been detected by MCD circuit but the detection can be delayed by 0.8192 msec. The delay of 0.8192 ms (8192 INTOSC1 cycles) comes from the 13 bit counter that's counting up (2^13 =8192) for more details encouraged to refer to TRM.
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