Ok. The code I uploaded doesn't have any drivers to go with for the host. It is serviced by writing the period to BUFPER data field and the duty cycles to BUFDCA, BUFDCB, and BUFDCC although these are buffered so if they are not updated the previous value is used. The code stays in a reset state and drives the pin values to 0 until a non-zero value is written to START's data field. The HET IDE project should have a trigger for this already at the 2us mark. The deadband applied to each pin can be written to BUFDBA, BUFDBB, BUFDBC although this shouldn't be changed after releasing the code from reset. There is a simple counter to count the period off - beginning of period pin goes low, middle of period pin goes high. It's done by alternating the mode of the ECMP at PERPIN with PERSET & CLR. Normally if the time base doesn't match one of these two points (beginning or middle of the period) then the code simply performs the comparisons (ECMP) for each pin. [PWMPINS] But if the period starts, the code goes to BUFPER to calculate the switching points for the next period. They are calculated as offsets to the counter value at the beginning of the period, the counter is never reset. Some of the compare registers for the second half of the symmetric PWM need so stay active into the beginning of the next cycle due the the way deadband works. That's why these ECMP instructions are not updated at the beginning of the period, they may not have yet triggered. These compare points get updated (written into the ECMP instructions) at the HPUPDATES point. TBASE1 CNT { comp=GE, reg=T, max=cntmax_lr, data=1FFFFFFh}; PERPIN ECMP {... reg=T, pin=PEROUT, action=CLEAR ,...cond_addr=PERSET, hr_lr=high, next=PWMPINS}; PERSET MOV64 {...reg=T, pin=PEROUT, action=SET, ...cond_addr=PERCLR, remote=PERPIN, ... next=BUFPER}; PERCLR MOV64 {... reg=T, pin=PEROUT, action=CLEAR, ...cond_addr=PERSET, remote=PERPIN, ... next=HPUPDATES}; The rest is mainly the math for computing the switching points taking deadband into account, and all of those compares. Each phase has 2 physical pins HI and LO. For each physical pins, there are 2 logical pins that are combined w. XOR. One of the logical pins controls the turn on time of the output, the other the turn off. The turn on is labled 'AHION' . The turnoff is labeled 'AHIOFF'. In the first half of the period, AHION and ALOOFF should trigger. In the second half, AHIOFF and ALOON should trigger.. except for some special cases where you are within a deadband of 0% to 100% then we may have to have two toggles in the same instant so that the XOR combination of them cancels and results in no pin change. There is also an independent compare point for the ADC trigger that can be placed anywhere within the period. (so you can give it a few cycles lead if you want to account for latency from trigger to start of convert.) -Anthony
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