If I were doing this task I might use Timer B. I would set up each individual pulse using ISRs. Because the output pulses cannot overlap, you have a natural limit to the performance requirements of the CPU.
Timer B allows latch-loading options that let you set up an entire pulse (both edges) in one ISR. Use output mode 4 (toggle). Make the first CCR write using CLLD_0, and make the second CCR write using CLLD_3, both in a single ISR execution. When a channel gives an interrupt, it has either started or ended a pulse. In the ISR determine if you should set up the next pulse now or wait for the next interrupt from this channel. (Be careful here.) Every channel driving an output has its interrupt enabled.
I would guess the timer would run in UP mode since that might simplify calculating match values. Calculations of match values should be done outside the ISRs.
It's about the same CPU overhead as you have now, but the output timing is perfect instead of being subject to interrupt latency like the current solution.
Jeff