The first block (6 lines) in SPI initialization, starting with > P6->OUT &= ~BIT3; as near as I can tell sets SCK low, then high, then low again. Setting the PSEL will bring SCK high again (so I guess that's 2 SCK cycles, not just 1). At that moment FSYNC (P9.3) is low from the initial sequence in main(), so the DDS is listening. P9.3 stays low until the end of the first transaction (in the ISR).
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