Hi Peter Thanks for your speedy reply... Sorry that I was not as clear as I should be. Stability issue... the devices locks up and requires a Reset to recover. It should of been PMM - Power Management Module (sorry dyslexia kicking in.. I should know by now to avoid acronyms ;)) The High Side and Low Side Monitoring and Supervisor is disabled under normal operation and in sleep. it is only enabled during the transition of the Mico VCC and VCORE i.e. From 2V to 3V3 (VCORE rise from lvl 0 to 2) and from, 3V3 to 2V (VCORE fall from lvl 2 to 0) After VCORE has gone to level 2, MCLK is increased (doubled), before the VCORE and VCC are reduced MCLK is halved. Here is a screen shot of VCC rising with VCORE I've looked at the library code and thought that it was being followed, with the modification of an exit condition if the transition takes too long, it was this modification that worried me... in that.. to cater for the additional code the CACHE would need to read from flash, it may not need to read from flash, if it was simply processing a while(bit set/clr); Many thanks
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