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Forum Post: RE: MSP430G2553 FSK: Delay between bits

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[quote user="Sai Vemprala"]Sorry, I don't follow. I am putting it in LPM0 and counting five cycles and then clearing LPM0 bits and calling the next (second frequency PWM) function. And if it's counting to 65535, why doesn't it happen when I have CCR values of 1000 and 500? Thanks[/quote]

I said what possibly can happen. What actually happens - it's up to you to find out. It's your code (which you did not show), not mine.

Well perhaps with increased cycle count you manage to change CCR value out of critical 500..1000 window - because of different CPU vs timer timing.


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