Part Number: MSP432E401Y I need to integrate an SPI device on a board revision (msp432e401y). It appears I will not have the opportunity to try it first, so I need to get it right the first time. The device expects /CS (Fss) to be asserted for the entire (many-byte) transaction. I want to make sure I can run it in Legacy mode, and I would prefer to connect Fss to the slave's /CS. It can run in either mode 0 or 3. Apparently "continuous back-to-back" [ref TRM 23.3.7.3 ff.] means "don't let the FIFO go empty", a dynamic requirement I'm not sure I want to agree to. If it comes to that, I don't mind connecting the slave /CS to a GPIO and wiggling that directly, but I need to know that at design time (i.e. now). I homed in on FSSHLDFRM. Amit Ashara seemed to confirm that I'm in the right vicinity: https://e2e.ti.com/support/microcontrollers/other/f/908/t/353108 My remaining concerns: 1) TRM (SLAU723A) Table 23-2 says that Legacy+FSSHLDFRM=1 is "Not a valid combination", followed by (paraphrasing) "This is what Bruce should use". In what sense is this combination "not valid"? 2) Amit Ashara's response suggests that I Must set FSSHLDFRM=0 Before transmitting (loading the FIFO with) the last byte. I foresee a certain amount of clumsiness. Does it still work if I set it to 0 after the last byte is sent? (Think /CS as a GPIO.) Thanks for any suggestions.
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