Many thanks Sunil. That would explain the performance difference. I've now found the section in the Cortex-R4 TRM (I was looking in all the TRM's apart from this one!!) and I think it indicates that for our use, configuring the peripheral registers as 'device' type memory is okay, but could you just confirm, in case I've misunderstood, that a read from 'device' type memory will only occur after any pending writes in the write buffer have completed? So any reads from device memory will always be coherent with preceding writes? And you were correct about our addresses for the peripheral register region - I didn't read our setup properly as we have that region divided into sub-regions so that it actually covers 0xFC000000 -- 0xFCFFFFFF and 0xFE000000 -- 0xFFFFFFFF. Best regards, Steve
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