Part Number: TMS570LS1227 We have a TMS5701227 acting as a 'flexray gateway'. We currently have the flexray operational with its transmitted and received data items being held in internal RAM, and we now need to complete the system design by moving these data items from internal RAM to an external RAM implemented as part of an FPGA. The problem we are having is with the external memory interface basically not providing the signals we expected, to identify the problem we added some test code (below), we also increased the SETUP, STROBE and HOLD times as suggested in another EMIF thread. Modified ASYNC setup : SETUP, STROBE, and HOLD fields in CE2FFG to maximum values emifREG -> CE2CFG = (uint32)((uint32)0U << 31U) | (uint32)((uint32)0U << 30U) | (uint32)((uint32)15U << 26U) | (uint32)((uint32)63U << 20U) | (uint32)((uint32)7U << 17U) | (uint32)((uint32)1U << 13U) | (uint32)((uint32)5U << 7U) | (uint32)((uint32)1U << 4U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)emif_16_bit_port); Modified PMU region 5 from DEVICE NON SHARED to STRONGLY ORDERED SHAREABLE and enabled sub regions 6 & 7 base address and size unchanged at 0x60000000 to 0x63ffffff ; Setup region 5 mov r0, #4 mcr p15, #0, r0, c6, c2, #0 ldr r0, r5Base mcr p15, #0, r0, c6, c1, #0 mov r0, #0x0000 orr r0, r0, #0x1300 mcr p15, #0, r0, c6, c1, #4 movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x19 << 1) + (1)) mcr p15, #0, r0, c6, c1, #2 Test Code (outline) U16 Val; volatile U16 * Loc; Val = 0x5555; Loc = ( volatile U16 * ) 0x60000000; ….. * Loc = Val; EMIF Results obtained Which appears to show the device is attempting some version of a 32 bit write, and with data different to that used by the code.
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