Part Number: TM4C1294NCPDT Tool/software: Code Composer Studio Started with a working CCS/Target/XDS100v3 and my projects are all working fine on the PC Brought in a similar project from coworker on the same target, built it locally, and tested target_config .ccxml (see report at the end of post) When I hit the debug button, CCS comes back with the complain Texas Instruments XDS100v3 USB Debug Probe_0/CORTEX_M4_0 : Target must be connected before loading program. What did I miss? Thanks for your time and help! _________________ Result from running Test Connection [Start: Texas Instruments XDS100v3 USB Debug Probe_0] Execute the command: %ccs_base%/common/uscif/dbgjtag -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity [Result] -----[Print the board config pathname(s)]------------------------------------ C:\Users\CHENWI~1\AppData\Local\TEXASI~1\ CCS\ti\0\1\BrdDat\testBoard.dat -----[Print the reset-command software log-file]----------------------------- This utility has selected a 100- or 510-class product. This utility will load the adapter 'jioserdesusbv3.dll'. The library build date was 'Oct 6 2016'. The library build time was '20:21:35'. The library package version is '6.0.407.6'. The library component version is '35.35.0.0'. The controller does not use a programmable FPGA. The controller has a version number of '4' (0x00000004). The controller has an insertion length of '0' (0x00000000). This utility will attempt to reset the controller. This utility has successfully reset the controller. -----[Print the reset-command hardware log-file]----------------------------- The scan-path will be reset by toggling the JTAG TRST signal. The controller is the FTDI FT2232 with USB interface. The link from controller to target is direct (without cable). The software is configured for FTDI FT2232 features. The controller cannot monitor the value on the EMU[0] pin. The controller cannot monitor the value on the EMU[1] pin. The controller cannot control the timing on output pins. The controller cannot control the timing on input pins. The scan-path link-delay has been set to exactly '0' (0x0000). -----[The log-file for the JTAG TCLK output generated from the PLL]---------- Test Size Coord MHz Flag Result Description ~~~~ ~~~~ ~~~~~~~ ~~~~~~~~ ~~~~ ~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~ 1 64 - 01 00 500.0kHz O good value measure path length 2 64 + 00 00 1.000MHz [O] good value apply explicit tclk There is no hardware for measuring the JTAG TCLK frequency. In the scan-path tests: The test length was 2048 bits. The JTAG IR length was 4 bits. The JTAG DR length was 1 bits. The IR/DR scan-path tests used 2 frequencies. The IR/DR scan-path tests used 500.0kHz as the initial frequency. The IR/DR scan-path tests used 1.000MHz as the highest frequency. The IR/DR scan-path tests used 1.000MHz as the final frequency. -----[Measure the source and frequency of the final JTAG TCLKR input]-------- There is no hardware for measuring the JTAG TCLK frequency. -----[Perform the standard path-length test on the JTAG IR and DR]----------- This path-length test uses blocks of 64 32-bit words. The test for the JTAG IR instruction path-length succeeded. The JTAG IR instruction path-length is 4 bits. The test for the JTAG DR bypass path-length succeeded. The JTAG DR bypass path-length is 1 bits. -----[Perform the Integrity scan-test on the JTAG IR]------------------------ This test will use blocks of 64 32-bit words. This test will be applied just once. Do a test using 0xFFFFFFFF. Scan tests: 1, skipped: 0, failed: 0 Do a test using 0x00000000. Scan tests: 2, skipped: 0, failed: 0 Do a test using 0xFE03E0E2. Scan tests: 3, skipped: 0, failed: 0 Do a test using 0x01FC1F1D. Scan tests: 4, skipped: 0, failed: 0 Do a test using 0x5533CCAA. Scan tests: 5, skipped: 0, failed: 0 Do a test using 0xAACC3355. Scan tests: 6, skipped: 0, failed: 0 All of the values were scanned correctly. The JTAG IR Integrity scan-test has succeeded. -----[Perform the Integrity scan-test on the JTAG DR]------------------------ This test will use blocks of 64 32-bit words. This test will be applied just once. Do a test using 0xFFFFFFFF. Scan tests: 1, skipped: 0, failed: 0 Do a test using 0x00000000. Scan tests: 2, skipped: 0, failed: 0 Do a test using 0xFE03E0E2. Scan tests: 3, skipped: 0, failed: 0 Do a test using 0x01FC1F1D. Scan tests: 4, skipped: 0, failed: 0 Do a test using 0x5533CCAA. Scan tests: 5, skipped: 0, failed: 0 Do a test using 0xAACC3355. Scan tests: 6, skipped: 0, failed: 0 All of the values were scanned correctly. The JTAG DR Integrity scan-test has succeeded. [End: Texas Instruments XDS100v3 USB Debug Probe_0]
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